45nm Technology and below
Samsung's 45nm low-power process technology is a continuation of the joint development initiative between IBM, Chartered and Samsung
Samsung's 45nm process is characterized by several key technologies.
- 193nm immersion lithography for patterning of critical design rules with defectivity rates comparable to dry litho systems
- Ultra low-k dielectric materials for metal line insulation results in RC delay reduction vs. low-k
Key Features of 45nm :
- Twin- or triple-well CMOS technology on p-substrate
- Shallow trench isolation
- Low-resistance nickel-salicided polysilicon and diffusion
- Four to ten copper metal levels, including up to six 1x, four relaxed-pitch 2x, and two relaxed-pitch 4x metal levels, one 6x metal level
- Wire-bond pads or controlled collapse chip connections (C4s)
- Optional electrically programmable fuses
