45nm low-power process technology is a continuation of the joint development initiative between Samsung Foundry and JDA alliance partners. Numerous products from top fabless players have been in mass production since 2008 enabled by 45nm low power process technology and its design ecosystem.
The 45nm process is characterized by several key technologies, which offers 193nm immersion lithography patterning of critical design rules with defectivity rates comparable to dry litho systems. Also, suggests ultra Low-K dielectric materials for metal line insulation resulting in RC delay reduction vs. low-k. The 45nm technology doubles gate density of the 65nm process with the significant low power and low manufacturing cost that is 50% linear shrink in addition to 15% speed enhancements and 35% active power reduction.
Key Features of 45nm
- Twin- or triple-well CMOS technology on p-substrate
- Shallow trench isolation
- Low-resistance nickel-salicided polysilicon and diffusion
- Four to ten copper metal levels, including up to six 1x, four relaxed-pitch 2x, and two relaxed- pitch 4x metal levels, one 6x metal level
- Wire-bond pads or controlled collapse chip connections (C4s)
- Optional electrically programmable fuses
|Core VDD (V)||1.1V|
|1.8V I/O Device||1.5V||•|
|2.5V I/O Device||2.5V||•|
|SRAM||Single Port||HS, HD|
|Dual Port||HS, HD|
* HS : High speed, HD : High Density