90/65nm Technology
90/65nm Process is a collaborative Technology Development Initiative between Samsung Foundry and JDA alliance partners. Samsung Foundry's 90/65nm process offers the most cost effective solutions for main stream products in market. 90/65nm Low Power technology covers a broad range of applications from the handheld devices to consumer electronics with the fully Si-proven Common Platform IP/Libraries which provides a variety of transistor, oxide and back-end stack options for customer's products.
Key Features of 90/65nm
- Twin- or triple-well CMOS technology on p-substrate
- Shallow trench isolation
- Low-resistance nickel-salicided polysilicon and diffusion
- Wire-bond pads or controlled collapse chip connections (C4s)
- Optional electrically programmable fuses
| Device Offerings | 65LP | 90LP | |
|---|---|---|---|
| Core VDD (V) | 1.2V | 1.2V | |
| Core Device |
HVT | • | • |
| RVT | • | • | |
| LVT | • | • | |
| I/O Device | 2.5V | • | • |
| 3.3V | • | • | |
| SRAM | Single Port | HS, HD | HD |
| Dual Port | HD | HD | |
* HS : High speed, HD : High Density
