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big.LITTLE Processing: Defining the Future of SoC Architecture

September 14, 2012

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Launched by ARM® in 2011, big.LITTLE processing is a popular topic of discussion in the semiconductor industry, drawing a lot of attention and even more questions about how the architecture works. Our Exynos line of processors uses big.LITTLE technology to achieve the optimal balance of high performance and significantly greater power efficiency, characteristics that are increasingly important to consumers in the market for tablets and smartphones.

Why is big.LITTLE architecture important?

We expect our smartphones and tablets to be capable of numerous functions that were once only possible on traditional PCs. From multimedia playback to running graphic-intensive applications, consumers demand high performance from their mobile devices. Thanks to advancements in technology that have drastically increased performance levels in mobile CPUs, the latest generations of smartphones and tablets have been able to meet these demands.

Pushing performance limits in mobile devices requires increasing the clock rates of the CPUs that run them, or using multiple cores within the CPUs or using both approaches at once. This resulting increase in performance, however, comes at a cost; high-performing CPUs consume considerably more power, resulting in decreased battery life for the mobile device.

Another important consideration is that battery capacities for mobile devices can only be increased to a certain point because of physical and form-factor constraints. The trends in today’s mobile device market favor thin, stream-lined smartphone and tablet builds, making increases in battery size, and thus increases in device dimensions, counter to consumers’ tastes.

big.LITTLE architecture by ARM® is a relatively new processor architecture designed to simultaneously support higher performance levels and lower power consumption in mobile CPUs, thus improving overall power efficiency. This particular architecture uses multiple cores within a CPU to efficiently execute high-intensity and low-intensity tasks as needed to achieve this end goal.

Omterconnect for Coherency

How does big.LITTLE architecture work?

big.LITTLE processing uses separate cores with different computing powers within the same CPU, as shown in this diagram. The more powerful core, or “big” core, handles intensive tasks, and the less powerful core, or “LITTLE” core, executes less intensive tasks. In this architecture, the “big” core is a Cortex™-A15 processor designed to achieve high performance, while the “LITTLE” core is a Cortex™-A7 processor built to maximize power efficiency.

The fact that these two separate cores are identical (other than differences in power efficiency) and are capable of handling the same tasks makes big.LITTLE architecture ideal for mobile devices, where conserving power is extremely important. In smartphones, for example, the “LITTLE” core is charged with handling basic, telephone-related functions, whereas the “big” core takes on more intensive, high-performance tasks, such as 3D gaming.

In order for such a system to be efficient, the time needed to transfer a task between the two core types should be minimized. By using a specially designed Cache Coherent Interconnect (CCI) to transfer data between cores, the system can switch tasks in the least amount of time possible. In fact, that window of migration time is short enough not to affect the performance speed of the application running on the system.

An additional benefit to the big.LITTLE architecture is its level of flexibility during the design process. Design engineers may decide how many “big” and “LITTLE” cores will be present within the CPU, with the current architecture allowing for up to four cores of both types. In this way, the designer has specific control over how the CPU will perform and can tailor it to the applications it is intended to operate.

Given the principles of big.LITTLE architecture and its many benefits, it’s easy to see why this technology is changing the industry’s approach to CPU design. Samsung is committed to designing high-performance, power-efficient SoCs that optimize mobile device performance, which is why we selected the big.LITTLE architecture by ARM® for our Exynos line of processors.

For in-depth explanations of the physical configurations of big.LITTLE architecture or its specific benefits over other processor architectures, please consult the resources below.

Additional big.LITTLE Resources

“Benefits of the big.LITTLE Architecture ,” by Hyun-Duk Cho of Samsung Electronics®

“big.LITTLE Processing with ARM® Cortex™-A15 & Cortex™-A7 ,” by Peter Greenhalgh of ARM®

For additional resources, visit the ARM® big.LITTLE Processing page.

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