Mobile Processor Basics: Interfaces
September 4, 2012
Our previous posts on mobile processor basics introduced readers to the basic functions of mobile application processors (APs) and their major components: the CPU, GPU and various sub-processors. In this post, we’ll delve into the important role of interfaces, using the Exynos 5 Dual as an example.
The Role of Interfaces
In the diagram shown at right, blocks with names followed by "I/F" represent interfaces, which connect two or more processing components and allow them to communicate with one another. Examples of common interfaces include USB ports, Ethernet connections and HDMI outputs. The interfaces used in Exynos mobile APs are specifically chosen not only for their high-speed performance but also for their power efficiency.
Display / Camera
This grouping of interfaces is responsible for several functions related to screen display and camera operation. This includes the 1080p HDMI v1.4 output and features that support WQXGA resolution, such as the integrated eDisplayPort® (eDP), a high-speed, low-power digital display interface.
The current Exynos lineup keeps the modem separate from the application processor. The modem interface links the Exynos 5 Dual’s AP with this discrete modem. Why keep the modem separate? Exynos engineers chose the AP, Modem dual-chip architecture because it still has significant advantages over single-chip solutions, such as faster time-to-market and lower manufacturing costs.
This particular modem interface houses a High-Speed Inter-Chip (HSIC), a USB chip-to-chip (C2C) interconnect that allows for high-speed data exchange between the chip’s DRAM and discrete modem. It also includes an MIPI High-speed Synchronous Serial Interface (HSI) v.1.1 that handles Wi-Fi and Wi-Fi display. With such high-speed communication avenues, the modem interface helps ensure that the Exynos 5 Dual doesn’t experience time lags when information moves between the AP and the modem.
The memory interface in the Exynos 5 Dual features a doubled datapath that supports better memory transactions than previous processors built on the Cortex™-A9 core. In fact, of all of the mobile APs in the Exynos line, the Exynos 5 Dual has the widest memory bandwidth (12.8 GB/s) due to its support of LPDDR3 , which offers higher memory densities and improved power efficiency. High memory bandwidth contributes to this chipset’s ability to smoothly and efficiently run graphic-intensive applications.
The Exynos 5 Dual supports multiple memory formats, including LPDDR and DDR3 , both of which offer better performance and memory density than earlier generation memory devices while also reducing power consumption. The memory interface also includes an Embedded MultiMediaCard (eMMC) v.4.5, a power-efficient memory system that assists the processor in low-level flash memory management.
The Exynos 5 Dual’s high-speed interface facilitates rapid communication between components, boasting a 2-channel USB HSIC supporting 480 MB/s with an on-chip Physical Layer (PHY).
Also included is a USB 3.0 Device or Host , also known as a SuperSpeed USB, that is backwards-compatible with USB 2.0. The USB 3.0 interface standard was developed to keep pace with advancements in computing capacity, speed and portability, making it ideal for mobile devices. With a max bandwidth of 5.0 GB/s and a greatly expanded power capacity, USB 3.0 takes mobile interfacing to the next level. Additionally, this interface standard allows for cross-communication between hardware and enables mobile devices to act as a USB device or host, thus increasing their usability.
The high-speed interface grouping also includes Serial ATA (SATA) III storage interface specifications. SATA III increases data transfer speeds between storage units, hard drives and host bus adapters to 6 GB/s, doubling the transfer rate of previous SATA specifications.
To learn more about mobile APs and how they affect smartphone and tablet performance, visit us on the Samsung Exynos website. Additionally, thank you to JEDEC for providing concise, updated information on “Global Standards for the Microelectronics Industry.”