Exynos 3 Single

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General Description

An application processor, or SoC (System on a Chip), is a microprocessor with a specialized architecture for deployment in embedded systems, such as digital still/video cameras, digital/smart TVs and set-top boxes, and automotive systems, among others. An SoC operates at frequencies from several hundred MHz to a few GHz, and is architected to deliver significant computing performances at low power consumption levels in limited board spaces. High-end SoCs often contain multiple cores, enabling them to deliver exceptional performances in applications such as digital imaging and multimedia devices.

Current-generation SoCs are capable of running full-fledged versions of modern operating systems, providing the user a rich, interactive interface on devices such as smartphones and tablet computers. Almost all the latest SoCs have the ability to decode a majority of multimedia codecs, and contain hardware engines to deliver enhanced multimedia experiences to the user. They also contain dedicated MMUs (memory management units) to manage the memory for applications being run on the device. Recent SoCs also have a multitude of peripheral connectivity solutions on the chip, offering the designer extensive control in providing connectivity options on the device. SoCs are application specific, and contain features targeted towards the intended deployment segment. Thus, an SoC designed for a mobile handset would include front-end GSM RF functionalities on-chip, which would be absent in an SoC designed for deployment in a digital still camera. An increasing number of SoCs, however, are now offering a wide range of features, making the processor suitable for deployment on any application. Samsung is a worldwide leader in providing the most advanced, efficient, and customizable SoC solutions for deployment on a wide range of platforms, such as digital imaging, multimedia, and mobile communication and computing. Samsung’s line of SoCs offers the highest performance, thermal stability, reliability, and I/O density in the smallest form factors at the lowest power consumption levels. Worldwide, Samsung is the preferred provider for SoC solutions for a majority of developers and OEMs for deployment on the broadest computing and communication devices and platforms.

Specifications

Exynos 3 Single is a 32-bit RISC cost-effective low power and high performance micro¡þprocessor solution for mobile phones and general applications. It integrates the ARM CortexA8 core which implements the ARM architecture V7-A with supporting peripherals.

To provide optimized H/W performance for the 3.xG & 4G communication services Exynos 3 Single adopts 64-bit internal bus architecture. This includes many powerful hardware accelerators for tasks such as motion video processing display control and scaling. Integrated Multi Format Codec (MFC) supports encoding and decoding of MPEG2/4 H.263 and H.264 and decoding of VC1 Xvid. This hardware accelerator (MFC) supports real-time video conferencing and Analog TV out for NTSC/PAL mode and HDMI for HD TV.
Exynos 3 Single has an interface to external memory that is capable of sustaining heavy memory bandwidths required in high-end communication services. The memory system has Flash/ROM external memory ports for parallel access and two dedicated DRAM ports to meet high bandwidths. Each DRAM controller supports LPDDR1 (mobile DDR) LPDDR2 or DDR2. Flash/ROM Port supports NAND Flash NOR Flash OneNAND SRAM and ROM type external memory.

To reduce total system cost and enhance overall functionality Exynos 3 Single includes many hardware peripherals such as TFT 24-bit true color LCD controller Camera Interface MIPI DSI MIPI CSI-2 System Manager for power management ATA interface four UARTs 24-channel DMA four Timers General I/O Ports three IIS S/PDIF three IIC-BUS interface two HS-SPI four SD Host and high-speed Multimedia Card interface USB Host 2.0 and USB Device 2.0 operating at high speed (480Mbps) with USB 2.0 PHY respectively and four PLLs for clock generation. POP (Package on Package) option with MCP is available for small form factor applications.


Detail Features
  • ARM CortexA8 based CPU Subsystem with NEON
    - 32/32KB I/D Cache, 512KB L2 Cache
    - 800MHz/1GHz Operating Frequency at 1.2 V and 1.25 V respectively
  • 64-bit Multi-layer bus architecture
  • Advanced power management for mobile applications
  • 64KB ROM for secure booting and 96KB RAM for security function
  • 8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224pixels for scaled and 8192 pixels for un-scaled resolution
  • Multi Format CODEC provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p@30fps and decoding of MPEG2/VC1/Xvid video up to 1080p@30fps
  • JPEG codec support up to 80Mpixels/s
  • 3D Graphics Acceleration with Programmable Shader up to 20M triangles/s, 1000Mpixels/s
  • Dedicated 2D Graphics acceleration supporting BitBLT, Alpha-blending, and Stretch function
  • 1/2/4/8 bpp palletized or 8/16/24bpp non-palletized Color-TFT, up to SXGA resolution
  • Composite TV-out interface with video amplifier and HDMI 1.3 interface
  • 4-lane MIPI-DSI and MIPI-CSI interface
  • One AC-97 audio codec interface and three PCMs serial audio interface
  • Three 24-bit IISs interface
  • One TX only S/PDIF interface support for digital audio
  • Three IICs interface support
  • Two high speed SPIs
  • Four UARTs up to 3Mbps port for Bluetooth 2.0
  • On-chip USB 2.0 Device supporting FS/HS (12Mbps/480Mbps, on-chip transceiver)
  • On-chip USB 2.0 Host supporting LS/FS/HS (1.5Mbps/12Mbps/480Mbps, on-chip transceiver)
  • Asynchronous Modem Interface support including 16KB DPSRAM
  • Four SD/SDIO/HS-MMC interface supporting SD Host 2.0, HS-MMC 4.3, SD Card 2.0, SDIO 1.0
  • ATA/ATAPI-6 compatible interface support
  • 24-channel DMA controller (8 channels for memory-to-memory DMA, 16 channels for Peripheral DMA)
  • Support 14x8 key matrix
  • 10-channel, 12-bit multiplexed ADC
  • Configurable GPIOs
  • Real time clock, PLL, timer with PWM and watch dog timer
  • Memory Subsystem
    - Asynchronous SRAM / ROM / NOR Interface with x8 or x16 data bus
    - NAND interface with x8 data bus
    - Muxed/Demuxed OneNAND Interface with x16 data bus
    - LPDDR1 interface with x16 or x32 data bus (266 ~ 400Mbps/pin DDR)
    - DDR2 interface with x16 or x32 data bus (400Mbps/pin DDR)
    - LPDDR2 interface (400Mbps/pin DDR)

Block Diagram

Samsung Semiconductor Block Diagram

Related Document

Product information is accurate at the time of publication.
However, subsequent product improvements may render some details inaccurate.