SAMSUNG ASIC Design Methodology and Services help you create a right-first-time multi-million gate ASICs on time. Our methodology and services not only help you create high-density, high-performance ASIC chips, but also help you merge "the-best-memory" in the world in your ASIC chip (eMemory). SAMSUNG ASIC Design Methodology can provide an efficient solution for multi-million gate ASICs in very deep sub-micron (VDSM) technology. For system-on-a-chip (SoC) designs, static verification methodology will shorten your design cycle time, which in turn will lessen today's ever-increasing time-to-market pressure. To deal with VDSM issues, the state-of-the-art, back-end CAD tools, both commercial and in-house, are supported. Our Design-for-Testability (DFT) methodology takes you through all phases of test insertion, test pattern generation and fault grading to get ultra-high test coverage. For a VDSM technology, interconnect delay can become dominant. Resistance shielding and the resulting effective capacitance effect for cell delay is important. SAMSUNG ASIC offers a the-best-of-both-worlds kind of solution that combines CubicDelay (SEC's common delay calculator) and Star-RCXT. SAMSUNG ASIC Design Methodology provide the IR-drop analysis and SI analysis and optimization.

SEC offers a Synopsys synthesis-friendly library. It contains primitive cells that implement design Compiler-frequently used combinational functions. By using synthesis-friendly cells, Design Compiler can give you a smaller and higher performance design.