display driver IC

reliability information

High Temperature Operating Life test (HTOL)

Purpose	Test method and Condition	Detectable failure mechanism	Related standards
To evaluate the resistance to electrical and thermal stress for a long period	Ta = 125˚C (Tjmax < 150˚C) Power supply = Operating max Dynamic	Ion contamination Oxide layer damage Broken junctions	MIL-STD-883E Method 1005.8 JESD22-A108-B EIAJED 4701 Test method 101

Early Life Failure Rate (EFR)

Purpose	Test method and Condition	Detectable failure mechanism	Related standards
To estimate the time dependant failure rate of process and product during initial customer use after supplier testing and screening.	Ta = 125˚C (Tjmax < 150˚C) Power supply = Operating max Dynamic 96hrs	Ion contamination Oxide layer damage Broken junctions ILT fail micro particles, dirt, and thin-film defects	JEDEC Standard No. 74, MIL-STD-883E Method 1015.9

High Temperature Storage (HTS)

Purpose	Test method and Condition	Detectable failure mechanism	Related standards
To evaluate the resistance to high temperature storage for a long period.	Ta = 150˚C	Via failure Kirkendall void	MIL-STD-883E Method 1008.2 JESD22-A103-B EIAJ ED-4701 method 201

Unbiased Highly Accelerated Stress Test (U-HAST) rature Operating Life test(HTOL)

Purpose	Test method and Condition	Detectable failure mechanism	Related standards
To evaluate with acceleration the resistance to storage and use in high temperature and humidity	130˚C , 85%RH 96hr 120˚C , 85%RH 96hr(LDI) 110˚C , 85%RH 264hr	Metallization corrosion	JESD22-A118

Temperature Cycle test (TC)

Purpose	Test method and Condition	Detectable failure mechanism	Related standards
To evaluate the resistance to the sudden change in temperature the device can experience during storage, transportation or, in use	-65~150˚C -55~125˚C -40~100˚C	Thin film metal deformation Cracked passivation bond wire fatigue failure solder bump fatigue failure	MIL-STD-883E 1010.7 JESD-A104-B EIAJ ED-4701/105

Latch Up

Purpose	Test method and Condition	Detectable failure mechanism	Related standards
To evaluate the endurance of a semiconductor device to "latch up" which is a temporary short-circuiting between the power source and the ground caused by lectric noise coming from I/O and power supply pins of a semiconductor device through a parasitic bipolar structure (SCR action) before a power supply is removed.	I-test : ±200ma(±100ma) V-test : 1.5 X max Vsupply	Soft(Function) Fail Vdd metal burn't Vss metal burn't Wire fusing & PKG damage	EIA/JESD 78 EIAJ ED-4701 Method306

Human Body Model(HBM)

Purpose	Test method and Condition	Detectable failure mechanism	Related standards
To evaluate resistance level and to establish test method of ESD, a model designed to simulate static electricity between semiconductor and static-charged human.	R : 1.5K Ohm, C : 100pF ±2.0KV	Junction filamentation Junction spiking	JESD22-A114-B ESD STM5.1-2001 MIL-STD-883E METHOD 3015.7

Machine Model(MM)

Purpose	Test method and Condition	Detectable failure mechanism	Related standards
To evaluate resistance level and to establish test method of ESD, a model designed to simulate static electricity of wrongfully grounded, } thus charged, machine.	R : 0 Ohm, C : 200pF ±200V	Junction filamentation Junction spiking	JESD22-A115-A ESD STM5.2

Charged Device Model(CDM)

Purpose	Test method and Condition	Detectable failure mechanism	Related standards
To evaluate resistance level and to establish test method of ESD, a model designed to simulate damage inflicted by self electrical discharge of electric field or triboelectric charged device due to contact with conductivity material.	Depending on device (Field Induced Method) ±500V	Metallization burn-out Oxide damage	JESD22-C101-A ESD STM5.3.1