That is impossible. On a cold reset (power on), the boot code copy operation is being executed automatically, and it is impossible to turn it on/off.

XiP boot can be executed within OneNAND since it has BootRAM. However, users can gain greater performance by downloading to DRAM and using it. So, aside from booting, OneNAND uses the SnD (Store and Download) scheme.

First of all, a user can read the Interrupt Register to verify the status of boot code completion. To use the INT pin, IOBE should be enabled, but the Interrupt register can be read regardless of the status of the IOBE. (It takes 70us to complete boot code copy.) Also, in the case of the MuxOneNAND, a user can recognize the completion of the boot sequence with DQ6 toggling. Only MuxOneNAND has a 'DQ6 toggle bit' function by which the user can verify the completion of an internal operation. When reading DataRAM that is in the process of being loaded, the DQ6 bit toggles. So, if the DQ6 stops toggling, the user knows that the loading operation (or booting operation) has completed.

The Data output will be unknown while the host reads the registers of the reserved area.

A Command-based operation is executed by issuing a command on the boot area address.
A program operation is not available with the command-based operation. A Register-based operation is the normal way of operating OneNAND. The address setting time may become a disadvantage of the register-based as compared to the command-based operation, but a wide variety of operations is executed with register-based operations.

After a boot-up, and when issuing LOAD, the first page of the first block will be loaded.
If executing a command-based operation immediately after a register-based operation, the page that is set by the FBA, FPA previously will be loaded. A continuous issue of this command will sequentially load data of the next page to dataRAM0. This page address increment is restricted within a block.

Since the BootRAM page size is half of the DataRAM page size, its spare area size is exactly 16 word (32 byte). So, a 32-word linear burst read operation is not supported on the spare area.

By setting the 'System Configuration 1 Register (F221h)', a user can operate OneNAND with synchronous mode. Although the default of OneNAND is asynchronous mode (RM=0), a user can have the device operate synchronously by changing the setting to RM=1.

No, users can read the 'Controller Status Register' in both asynchronous and synchronous modes.

Error correction is available only on a load operation. The following table illustrates the differences in the error correction of the main area and spare area.

*2 nd word and LSB of 3 rd word

If it is a 1-bit error, it is corrected automatically by H/W ECC. If it is 2-bit error, it is reported to the OS and then it waits for the next action of the OS.

When a user wants to copy a block to an empty block, they should read the block and write it back to the empty one. It takes longer and uses more current than the internal copy-back operation. Since the device can execute both 1-bit ECC & 2-bit EDC during copy-back operations, the integrity of the data is guaranteed. OneNAND also supports 'Copy back with random input' operation. Host can modify on DataRAM with this function during copy-back operation. Please refer to datasheet for further information.

After the MBE, the 'Erase Verify Read' operation is executed. So, users can tell if the erased blocks are protected ones by reading the Lock bit (DQ14) of the Controller status register (F240h) during the 'Erase Verify Read' operation.

Conditionally yes. Once the Cold/Warm/Hot resets on the device during Erase suspend, it cannot go back to the 'Erase Resume' operation. But OneNAND should be reset to exit from the 'OTP Access mode'. Therefore, to keep the 'Erase Suspend mode' only 'NAND Core reset' is available, even while exiting from the 'OTP access mode'. If users want to return from the 'OTP access' to the 'Erase Resume', they have to issue a NAND Core Reset and then operate Erase Resume.

It is impossible. The suspended address cannot be read although the device knows the address internally.

Multi Block Erase operation is available within a chip. DFS and DBS should be fixed before setting target blocks.

There are 4 kinds of Reset commands in OneNAND. They are Cold Reset, Warm Reset, Hot Reset, and NAND Flash Core Reset. For further details, please check the 'Reset Mode Operation' section in our data sheet.

Yes. It takes tREADY2(10us~500us) to complete a reset operation. After tREADY1(5us) from reset initialization, RDY goes high. While RDY is high, BootRAM can be read, although the INT is low. That is, the host can read ONBL1 before the completion of a Warm Reset. The host can read ONBL1 during a Hot Reset as well.

A INT pin indicates the completion of internal operations such as program, load and erase. Interrupt register (F241h) plays the same role as the INT pin. But when the host employs the interrupt register to verify an internal operation completion, the host must periodically monitor the 'Interrupt register'. This is called 'polling'. Although the host issues a command while INT is low, the command is ignored. When the host issues the command, the host must write '0' to the 'Interrupt register'. Since there is an INT auto mode in the 1Gb A-die, the host doesn't have to write '0' to the 'Interrupt register' manually with these products. (In case of INTpol=0, the host has to write 1 'Interrupt register' before issuing command.)

The host notices the completion of an internal operation when the INT reverts to ready. If the host doesn't set INT to low, then the host will not recognize that the internal operation has completed. Furthermore, the next operation that the host commands is not guaranteed to work, because the previous operation may not have finished by this time. Therefore, the host must write 0 to the 'Interrupt register' and wait for the system to revert back to ready.

Yes. Generally, error checking is performed by checking 'Controller Status Register (F240h)' after the entire operation has completed. So, INT will go back to ready regardless of the instances of operation error.

Yes. The INT pin can be replaced with the 'Interrupt register (F241h)'. However, if users wish to use the 'Interrupt register', they should perform a polling of the register with the software. In case of RDY, if a chipset supports a non-handshaking mode, the RDY can be replaced by setting the BRL in the 'System Configuration 1 Register' to catch all initial data.

This is related to setting the OTP lock. The 8th word of a sector0/page0 of the OTP block is assigned for the OTP lock bit. So, it is set aside as a reserved area so that the user cannot write to it.

Since the OTP block is separated from the NAND core, the host should issue an 'OTP access' command in order to access the OTP block. In the OTP block, the host technically cannot erase data within the block because the erase fuse is cut by the manufacturer.
To lock the OTP block, the host must program two bits on a specific area guided by the datasheet. Once the OTP locked, the block isn't programmable or erasable. On the other hand, when locking a normal block, the host has to follow the 'Write protection operation' procedure guided by the datasheet. The block could be either an 'unlock', 'lock' or 'lock-tight' state by the internal circuit, depending on the procedure. Therefore, it takes 220us(tPGM) to lock the OTP block while it takes 500ns(tLOCK) to lock a normal block.

There are three kinds of OTP operations. They are 'Load', 'Program' and 'Lock'. And there are two kinds of 'FBA setting' steps on the 'Program' and 'Lock'. The common FBA setting could be omitted or any address, and is the first FBA setting on the flow charts. This is a part of the command sequence that is set but it's not related to setting the actual address. The second FBA setting step, which is not in 'Load' but is in both 'Program' and 'Lock', cannot be omitted. In this FBA setting step, the FBA should be directed to only unlocked block of the NAND array. Even though this FBA actually doesn't point to the OTP block, but this step is required to operate properly.

Basically, the OTP block is a valid block for its entire lifetime. Most cases of bad blocks take place in cases when the blocks are programmed and erased iteratively.
But the OTP block is predominantly used to read. So, it is unlikely to become an invalid block.