FAQs
We can support industrial temperature ranges if there are any requests. Please contact the Sync SRAM manager of each branch or HQ directly.
We're open for the inquiries and will be happy to support our customers' questions and concerns.
Some devices need to be implemented in harsh, inclement weather conditions. To enable our products to work well in these conditions, we manufactured the parts to work with a broader temperature range.
| Operating Temperature | |
|---|---|
| Commercial | 0 ~ 70 °C |
| Industrial | -40 ~ 85 °C |
It depends on the products. If your order is in stock, we can shorten the lead time. If not, it can take from 4 weeks to 12 weeks, so please contact local sales representatives for an accurate lead time.
Please check the table below for comparisons.
| Desing Issue | QDR I | QDR II | QDR II+ | |
|---|---|---|---|---|
| Frequency Maximum |
B2 | 167 MHz | 250 MHz | None |
| B4 | 200 MHz | 333 MHz | 450 MHz | |
| Frequency Minimum | None | 120 MHz | 120 MHz | |
| DLL | No | Yes | Yes | |
| Initial Latency | 1.0 clock cycles | 1.5 clock cycles | 2.0 clock cycles | |
| Clocks | No echo clocks | Echo clocks | Echo clocks | |
| Data Valid Window |
1.4 ns @ 167 MHz (47%) | 960 ps @ 333 MHz (64%) | 555 ps @ 450 MHz (50%) | |
| Density | 9 Mb / 18 Mb / 36 Mb | 18 Mb / 36 Mb / 72 Mb | 18 Mb / 36 Mb | |
| Interface | HSTL 1.5 V or 1.8 V ClassⅠ | HSTL 1.5 V or 1.8 V ClassⅠ | HSTL 1.5 V ClassⅠ | |
| Power Supply | 2.5 V | 1.8 V | 1.8 V | |
| Package | 165 BGA | 165 BGA | 165 BGA | |
The 10th digit of part number indicates die version. It starts with M, followed by A. Further die version follows by alphabetical order. You can assume that a later die version can cover a preceding die version.
For example, the characteristics of D die version can cover them of C die version. So, if you used C die version before, you can use D die version without difficulties. For further information, please contact local representatives.
Please refer to “ Part Number Decoder (Ordering Information)” in our site.
As the NC pins are internally really NC (not connected), it is possible to mount floating or grounding. However, in cases where DQ pins are used for a special purpose, we recommend you to mount floating.
There is no low speed limitation among our High speed SRAMs (Async.Fast/NtRAM/SB,SPB/QDRII/DDRII) except QDRII/DDRII products which use DLL. In the case of QDRII/DDRII products, clock cycle time is limited to Max. 8.4ns (approximately 120MHz) to guarantee the DLL completion. However, if QDR mode is used at low speed, you can use QDRI mode by turning DLLoff.
For details, please refer to Application note (User guide of QDRII as QDRI) on the web site.
In case of Address pin (ball), user can decide the sequence manually and use it. (Exception of Burst address pin(ball))
Unfortunately, we do not support VHDL model. Instead, please refer to the Verilog model which is relevant.
