New Technology
IEP Technology
IEP's General Information and SEC Status
- Embedded Technology and PoP
- - Enable use standard memory package
- - Flat top surface Can increase interconnection IO between memory and embedded ASIC package
- IEP Structure and Key Technology
- - Chip bump which interconnect to PCB via
- - Thin Chip attach on IEP
- - Fine pitch Via, Line/ Space
- - Warpage control (IEP Process, BLR)
- Development Plan and Target
- - 1st Function sample delivered ('07.06)
- - Reliability evaluation (TBD) - co-work with PCB Vendor
- - Performance Characterization (TBD)
