Key Features of 45nm.
- Twin- or triple-well CMOS technology on p-substrate.
- Shallow trench isolation.
- Low-resistance nickel-salicided polysilicon and diffusion.
- Four to ten copper metal levels, including up to six 1x, four relaxed-pitch 2x, and two relaxed- pitch 4x metal levels, one 6x metal level.
- Wire-bond pads or controlled collapse chip connections (C4s).
- Optional electrically programmable fuses.