Foundry

Each new process node has its own set of challenges but a 20nm system on chip device may be the most difficult as it requires an entirely new approach to the design infrastructure. To address these new challenges, Samsung has spent considerable time developing a robust design ecosystem to complement the process technology. The result of that effort was an initial 20nm test chip tape-out where new design kits, router and other design enablement features were used to support novel process innovations such as new device structures, local interconnects and advanced routing rules. The investments that Samsung is making now will allow customers to have broad access to all aspects of the design and process infrastructure when they’re ready to begin a 20nm project.

From the outset, Samsung Foundry began developing the design enablement along side the process to ensure that all the pieces where in place when customers were ready to begin their 20nm system-on-chip (SoC) designs. For the 20nm test chip, Samsung with its ecosystem partners – ARM, Cadence Design Systems and Synopsys – implemented a broad suite of design collaterals. ARM physical IP and processor IP were used to build a prototype SoC test chip. Samsung utilized both Cadence unified digital design flow and the Synopsys Galaxy Implementation Platform to implement different components of the test chip in order to validate Samsung’s design methodology for both Cadence and Synopsys design flows.

Samsung Foundry’s early access process design kit (PDK) is currently available to those customers who are in the initial stage of designing their next-generation SoCs.

Samsung Foundry’s focus for the 20nm technology generation is to maintain the same increases in performance, power efficiency, and density that have been possible moving from 45nm to 28nm with the addition of HKMG. Samsung’s 20nm technology will be a full node shrink from 28nm, enabling the ~50% area scaling that the industry has come to expect with each technology generation. The technology has been designed to allow Samsung to maintain its leadership in die size and cost, which remain critical factors for customers at leading-edge nodes. Key technology features include:

• Planar CMOS technology using a Gate Last approach to High k Metal Gate (HKMG)
• 193nm immersion lithography supplemented by source-mask optimization
• Constrained minimum pitch to reduce the need for time-consuming, costly double-patterning
• Second-generation ultra-low k dielectrics to lower power dissipation by reducing interconnect capacitance and wiring delay
• Innovation with local interconnect and self-aligned vias to achieve cell-level scaling and elimination of a metal layer
• Fifth-generation strained silicon technology for power and heat reduction and more efficient switching

At 20nm, lithographic capability will drive restrictive design rules independent of the choice of Gate First or Gate Last, which means other factors play a larger role in the choice of materials integration. Samsung has actively evaluated multiple materials schemes and determined that a Gate Last approach to High-k Metal Gate (HKMG) will best suit the needs of customers at 20nm.

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