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32nm LP HKMG Process Node
"Samsung's announcement that it has qualified and ramped up its 32nm high-k/metal gate architecture – to be followed quickly with a 28nm version -- has the industry buzzing about the reshaping of leading-edge semiconductor foundry manufacturing."
- Stephen Woo, Executive & GM, Samsung
32nm 28nm 20nm
32nm LP High-k Metal Gate First Process
Samsung’s 32nm LP HKMG Process Node has been a proven volume production process since mid-2010. This was the industry’s first 32nm LP HKMG logic process to be qualified, and was designed for a remarkably simple migration path to the 28nm node.
The 32nm process is a gate-first High-K Metal Gate process. Jointly developed with IBM, the gate-first approach enables it to deliver twice the logic density of 45nm processes while maintaining low power, making it ideal for mobile applications
32nm Low-Power High-k Metal Gate Processes
When compared to Samsung’s 45nm process, the 32nm LP HKMG processes offer designers the flexibility of lower power at the same frequency or higher performance.
32nm vs. 45nm
 
32nm LP HKMG
Active Power
41% less
Performance Boost
27% more
Material Science
HKMG, High-K Metal Gate process first developed by Samsung, IBM, and other partners in 2007 as a way to improve performance and reduce transistor gate leakage at reduced geometry process nodes. Conventional Ploy/SiON material is replaced with High-k material to continue gate dielectric scaling (Tox/Tinv).
In Samsung’s Gate-First HKMG process, the transistor’s gate stack is fabricated first, followed by source and drain. This more cost-effective approach facilitates superior area scaling and preservation of layout rules without complex design rules.
Samsung's 32nm Gate-First HMKG Process Features
2x gate density increase compared to 45nm
Over 100x lower gate leakage
Greater than 40% delay improvement at fixed leakage
10X leakage reduction at fixed speed
Process Development Kits
Process Development Kits are available for the 32nm LP Process. PDKs include:
SPICE models
DRC
LVS
Parasitic Extraction
Base and MS/RF
RFDE/ADS
Ground and DFM-based P-Cells
Design Enablement EcoSystem
Samsung Foundry processes are developed on years of semiconductor manufacturing leadership and IC design experience. We have forged alliances with leading EDA Tools and IP Libraries providers for our processes to enable you to realize your design and manufacturing objectives as efficiently as possible.
32nm Node EDA Tools
Physical and Processor IP Libraries
Applications
Low power and tight power budgets, always required in mobile applications, is now a concern across a wider set of devices for communications, networking, servers, and data centers. The Samsung 32nm process delivers low power, high bandwidth, and advanced integrated functionality for these demanding applications.
Smartphone
Tablet
Internet TV
Design
Services
Samsung offers comprehensive design services, IP, and libraries.
B2B Portal