February 25, 1999 in Social Responsibility News

SAMSUNG Electronics Presents Paper on Superfast Semiconductor Technology at ISSCC, San Francisco

Seoul and San Francisco - February 25, 1999 - At the International Solid-State Circuits Conference (ISSCC) held in San Francisco, February 15-17, Samsung Electronics Co., Ltd. presented the 1-Gigabit Double-Data-Rate (DDR) SDRAM, quickly emerging as the next generation super-fast DRAM. Sponsored by the Institute of Electrical and Electronics Engineers (IEEE), the ISSCC is now the most authoritative international academic organization in the semiconductor field, with over 10,000 members from twenty-five countries. Samsung's paper details the application of new technology to enhance the performance of next-generation devices. The new technology is employed and tested using 0.14-micron design rules, which are the smallest ever achieved. Highlights of the technology are:

Enhanced Speed
The 1-Gigabit Double-Data-Rate (DDR) SDRAM with 0.14-micron technology and pipelined data path technology results in enhanced bandwidth of up to 333-megabit per second per pin. The new technology provides an adaptability to the clock cycle time, enabling the maximum clock rate operation for high performance, and the scalable internal timing margin for improved tolerance to processing variations. Devices can transmit 264 million characters a second, at least triple the speed of the fastest memory devices used in PC100 SDRAM technology.

Low Power Consumption
With this new technology, memory devices will be able to operate on just 2.5 volts, a 25% reduction from the 3.3 volts previously required. The reduced voltage, however, does not compromise performance. Thus, the device becomes suitable for high-end computing systems with less power consumption as well as for low-end portable applications with increased battery-operating hours.

Precise and Fast Clock Generation
Application of Delay-Locked-Loop technology with digital and analog control circuitry makes possible for a fast-locking cycle and precise jitter control. Being an essential circuit for DDR operation, this cikrcuit provides the specified timing accuracies within 0.45ns for all data pins operating at 333Mbps.

New Package Solution
The multi-layer chip scale package greatly enhances the device in achieving high performance through small skew and small data flight time and standard compliance through flexible package pinout adaptability. Hence, the new technology enables next-generation devices to be fully backward-compatible with standard lower-density memories.

Background
Demand for high-speed memory devices has soared since the rapid advances in hardware and software operating systems, notably with the introduction of Intel's Pentium II and Microsoft's Windows 98. Super-fast devices are expected to represent 50% of the world semiconductor market by 2001. Samsung's memory portfolio includes DDR, Rambusa and Synchronous products. The Joint Electron Device Engineering Council (JEDEC) has accepted DDR as a new standard, and these devices are expected to be used initially in servers and workstations that require high-speed data processing.

Samsung Electronics Co., Ltd., with 1998 sales revenue of more than 17 billion dollars (US), is a world leader in the electronics industry, with operations in more than 50 countries and 60,000 employees worldwide. The company consists of three main business units: Multimedia & Home Appliances, Semiconductors and Information & Telecommunications. For more information, please visit our website http://www.samsungelectronics.com

Rambus is a registered trademark of Rambus Inc. All other trademarks are property of their respective owners.


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