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Efforts towards energy efficiency: Semiconductors

Semiconductors

In 2022, DS Division established a plan to reduce power consumption in memory products and has continuously made efforts to achieve this goal. Building on these efforts, we are supplying HBM41) and PM17632) in a timely manner, with improved power efficiency features over previous generations.
Going forward, we will continue our efforts to improve power consumption relative to data processing performance by developing products that incorporate differentiated technologies beyond process scaling. Leveraging our integrated semiconductor capabilities across memory, foundry, and advanced packaging, we have set targets to improve the energy efficiency of HBM and server SSDs by 2.5 times and 4 times, respectively, by 2030 compared to 2025 levels. Through these efforts, we will continue to provide optimized solutions for customers' next-generation AI infrastructure.

We are also reducing the power consumption of our non-memory products. The Exynos 2600, based on the industry's first 2nm GAA3) process, integrates a powerful CPU, NPU, and GPU4) into a single compact chip, delivering a new and enhanced mobile experience with less energy. Furthermore, we are contributing to improved power efficiency through process technology innovation. To reduce power consumption during our customers' manufacturing phase, we have improved our process-level energy efficiency by utilizing EUV5) processes to form fine patterns and adopting GAA transistors in ultra-fine processes of 3nm or smaller to stably lower operating voltages.

  • 40% improvement in power efficiency compared to the previous generation (HBM3E)
  • 60% improvement in power efficiency compared to the previous generation (PM1753)
  • Gate-All-Around, next-generation transistor structure technology
  • Central Processing Unit, Neural Processing Unit, Graphics Processing Unit respectively
  • Extreme Ultraviolet

  • Memory Semiconductors

    DRAM

    Mass production of HBM4 based on 1c DRAM

    By integrating 1c DRAM (Samsung’s 6th-generation 10nm-class DRAM) and the most advanced 4nm foundry process, Samsung Electronics has secured industry-leading performance while improving power efficiency and thermal characteristics, providing an optimized solution for next-generation AI infrastructure.

    • Improved power efficiency by 40%, thermal resistance by 10%, and heat dissipation by 30% compared to the previous-generation HBM3E through low-power core die design and power distribution optimization.
    • Achieved an operating speed of 11.7 Gbps (up to 13 Gbps) and a maximum bandwidth of 3.3 TB/s, exceeding JEDEC1) standards.

    SSD

    Mass production of PM1763, a PCIe2) Gen6-based SSD for servers

    By adopting PCIe Gen6 with a controller based on a 4nm process, Samsung Electronics provides a high-performance storage solution optimized for AI and HPC workloads, delivering industry-leading performance and improved power efficiency.

    • Improved power efficiency by 60% compared to the previous-generation PM1753 through controller optimization and design improvements.
    • Achieved sequential read speeds of 28,400 MB/s and sequential write speeds of 21,000 MB/s, providing a data transfer bandwidth more than double that of the previous generation.
    1. Joint Electron Device Engineering Council
    2. Peripheral Component Interconnect Express

  • System Semiconductors

    Exynos Modem

    We achieved an approximately 40% reduction in modem standby current during smartphone idle states compared to the previous model.

    • Applied technology to reduce DRAM access frequency and usage during standby operation.
    • Reduced the time required to re-enter standby mode by parallelizing multi-core CPU operations when processing paging data during the wake-up period.
  • All product specifications reflect internal test results and may vary depending on the user's system configuration. Actual performance may differ based on usage conditions and environment.
Last updatedJune 26, 2026