The easy guide to a semiconductor: Why the 10nm FinFET Process?

May 10, 2017

The Samsung Galaxy S8 and S8+ come with numerous innovative features to bring the mobile experience to the new level. Notably, the Galaxy S8 and S8+ are powered by the Exynos 9 Series (8895) processor built on the advanced 10nm FinFET process for superb performance and long lasting battery life.

So, what does "built on the 10nm FinFET process" mean?

Understanding the manufacturing process of a semiconductor chip can be very difficult and confusing. There are numerous steps involved for not just manufacturing the chip but also for making improvements in performance and power efficiency. Since 2009, Samsung has been delivering more powerful and power efficient Exynos Processor every year. How is this possible? Let’s find out.

The transistors & process nodes
A mobile processor is the heart of your mobile device. It’s consisted of numerous transistors that are built with semiconductor materials such as a silicon. Transistors are a fundamental element for building modern electronic devices like smartphones. Just like a light switch, they control the power flow in a binary form of “0” and “1”, where 0 is off and 1 is on. To run an application, a mobile processor computes numerous outputs of “0s” and “1s” generated by billions of transistors.

Within the transistor, electrons move from a source to a drain through a channel under a gate. The gate, which works as a switch, allows a transistor to control the flow of electrons with on-off instructions.

For a gate to control the on-off instruction sets, a gate oxide is needed. Gate oxide is a dielectric layer that blocks the movement of electrons from a source to a drain when “off”, and attracts when “on”.

Illustrative image showing fabrication of the conventional transistor

You may already be familiar with the fabrication nodes like 20nm, 14nm, and 10nm process. The numbers indicate the length of the gate (Lg) that is related with the distance between the source and the drain. As we shrink the fabrication nodes, the length of the gate or the electrons’ path gets shorter. With a shorter path, a chip like mobile processor can operate faster as the electrons only need to travel shorter distance to operate. Also a shorter distance means less power required to travel thus enabling the mobile processor to be more power efficient.

The thickness of the gate oxide layer also has large impact on the operation speed. While thinner gate oxide layer enables the gate to work faster by using lower amount of voltage, it could increase the current leakage when in “off” status. Although the amount of current leakage within a single transistor can be very minute, it could be a big problem for a mobile processor as it is usually built with billions of transistors.

Changes in Gate Material: From Polysilicon to High-K Metal
As the process node shrinks further, not only the path gets shorter but also the thickness of the gate oxide gets thinner. Unfortunately silicon dioxide gate dielectric (SiO₂), a conventional gate oxide, has its limitation in insulation effect with thickness below 2nm. So semiconductor companies replaced SiO₂ gate oxide with High-K to reduce current leakage. In addition, to increase the sensitivity of the gate, a poly-Si material was replaced with a metal. With High-K Metal Gate or HKMG as a gate material, a transistor is able to deliver faster gate operation with reduced current leakage even with thinner gate oxide.

Illustrative image comparing fabrication of the Conventional Silicon Transistor and High-K Metal Gate Transistor

The HKMG transistor solved the current leakage problem with thinning gate oxide. However, with further shrinking of the fabrication process beyond 14nm, the changes of gate and gate oxide technology wasn’t enough to efficiently control the current leakage.

Changes in Gate Structure: From 2D Planar to 3D FinFETUp until 20nm process, the transistors were built in 2D planar structure. In planar structure, the gate sits on top of a single surface of a channel in between the source and the drain. While this structure served its purpose, its 2D shape held back performance and efficiency of fabrication process beyond 14nm.

To solve the limitation of the 2D planar, the transistor was redesigned in to a 3D FinFET structure. In a fin shaped 3D FinFET structure, there are three surfaces of a channel that are wrapped around with the gate for efficient leakage control.

In addition to the new structure design, an improvement in controllability allows the gate to switch on-off using lower voltage. With lower VDD(Voltage Drain Drain), subthreshold swing, a slope from “Off” status to “ON”, can be reduced thus allowing the FinFET structure to switch On/Off using less energy than the planar structure.

Illustrative image of 3D FinFET structure

Power efficiency is not the only advantage of the FinFET technology. In planar structure, electrons move from a source to a drain through just one surface under the gate, whereas in FinFET structure, electrons can move across three surfaces of the fins-shaped 3D structure increasing the drive strength or the amount of moving electrons. Notably, a shorter gate length of the 14nm process means much faster on/off switching as electrons move shorter distance from a source to a drain. So if the channel is a road, the number of lanes increased by three folds while the length needed for electrons to travel is shortened in 14nm FinFET structure when compared to 20nm planar structure. With more electrons moving faster through the channel, one can simply expect much improvement in performance.

As a result, FinFET process is able to achieve the highest levels of efficiency and performance. When compared to a 20nm HKMG process technology, a 14nm FinFET process enables up to 20 percent improvement in performance or 35 percent less power consumption. A 10nm FinFET process, a technology used in the recently announced Exynos 8895 processor, delivers up to 27% higher performance or 40% lower power consumption than 14nm FinFET LPE process. Furthermore, Samsung’s advanced structure technology enables aggressive scaling of the gate pitch, a space between the edges of adjacent gates, to further minimize the chip size.

The Exynos 9 Series (8895) built on a 10nm FinFET Process
In 2015, Samsung introduced mobile application processor, The Exynos 7 Octa (7420), built using the 14nm FinFET technology for the first time in the industry. The Exynos 9 Series (8895), a 10nm FinFET processor announced in February of 2017, is currently powering up the new Galaxy S8 and S8+. This ground-breaking accomplishment is a result of Samsung’s unparalleled R&D efforts in FinFET technology since the early 2000s. Starting with a research article presented at IEDM (International Electron Devices Meeting) in 2003, Samsung has continuously made progress and announced its technological achievements in FinFET research and filed a pool of key patents in the related field.

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