DDR5: Breaking the bandwidth barrier
on Jan 31, 2020
The spec sheets of modern computers are proof of just how far the march of technological progress has come in the last decade. From new form factors that have allowed manufacturers to create more portable devices to improved clock rates and memory speeds, improvements in computing power have opened opportunities to develop new products and services. Now DDR5 (Double Data Rate 5) SDRAM, the latest development in memory, will help unlock a new level of performance.
The successor of DDR4, DDR5 is the next generation of synchronous dynamic random-access memory (SDRAM). DDR memory can send and receive data signals twice during a single clock cycle and allows for much faster transfer rates and higher capacities.
While most of the developments in DDR memory have been modest increments with a focus on performance improvements to meet server and PC application requirements, the jump from DDR4 to DDR5 is a much bigger leap forward. Driven by a need for more bandwidth, DDR5 brings a completely new architecture in a powerful package.
Rising to the Challenge
The rapid development of computing power has seen CPU manufacturers battle to deliver the highest core counts. Not long ago, PC users could expect about 4-cores. Now, most CPU manufacturers offer 6-cores in their mid-range chips and 12-cores in their high-end, prosumer level products. For server solutions, they offer as many as 64 cores. Current server memory solutions, such as DDR4, fall short of meeting the bandwidth demand of these high-core-count CPUs.
Signal integrity, power delivery, and layout complexity have limited the progress in memory bandwidth per core. Unlocking the power of next-generation CPUs requires new memory architectures that can step up to their higher bandwidth-per-core requirements. This has been the main drive in developing DDR5 SDRAM solutions.
Next-Generation Power and Efficiency
To meet the demands of next-generation CPUs, DDR5 brings much higher data rates, lower power consumption, and increased density. At launch, DDR5 featured a maximum data rate of 4800MT/s, compared to 3200MT/s of DDR4. Side-by-side comparisons in system-level simulations show that DDR5 has approximately 1.87 times the effective bandwidth of DDR4.
DDR5 increases burst length to BL16, about double that of DDR4, improving command/address and data bus efficiency. The same read or write transaction now provides twice as much data on the data bus while limiting the exposure to IO/array timing constraints within the same bank. Additionally, DDR5 doubles the number of bank groups, a key factor in improving overall system efficiency by allowing more pages to be open at any given time. All of these factors mean faster, more efficient memory to meet the demands of next-generation computing. But DDR5 isn’t just improving performance, it’s also delivering improved scalability.
Scalability for Next-Gen Computing
Optimized DRAM core timings and On-die error correction code are the two main factors improving scalability for DDR5. While memory architectures continue to scale year over year, it comes at a cost including drops in DRAM cell capacitance and increasing contact resistance in bit lines. DDR5 addresses these drawbacks and allows for more reliable scaling with optimized core timings that are critical to ensure adequate time to write, store and sense charges in the DRAM cell.
On-die error correction code (ECC) improves data integrity and reduces the system error correction burden by performing correction during READ commands prior to outputting the data. DDR5 also introduces an error check scrub where the DRAM will read internal data and write back corrected data if an error occurs.
Samsung Delivers the Future of Memory
Leveraging Samsung’s cutting-edge memory innovations, the company has developed DDR5 that provides powerful, reliable performance capable of handling the ever-increasing demands of modern servers.
With maximum data transfer speeds of up to 4,800Mbps, Samsung’s DDR5 is designed to handle heavy workloads. To maximize storage capacity, Samsung’s DDR5 uses the company’s latest TSV 8-layer technology, allowing a single chip of DDR5 to contain twice the number of stacks compared to DDR4. Each DIMM also provides up to 512GB of storage. Samsung’s DDR5 also features an Error Correction Code (ECC) circuit to enhance reliability, making it an industry-leading memory solution.
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