Versal: New Xilinx Adaptive Compute Acceleration Platforms
Nov 05, 2018
Versal is a brand new 7nm SoC family from Xilinx which adds impressive computational capabilities to FPGAs. This talk covers the overall system architecture for devices which includes the ARM cores (scalar engines), programmable logic (Adaptable Engines) and vector processor cores (AI engines). The role of the AI engines will be illustrated to show the architecture, the integration in the total device, and some key application domains such as Machine Learning and 5G wireless. The early design rationale and the cooperation between Research Teams and Product teams were critical to deliver this innovative programmable platform.
About the Speaker
Kees Vissers is a Xilinx Fellow. He graduated from Delft University in the Netherlands and led efforts at Philips Research on Digital Video systems, HW–SW co-design, VLIW processor design and dedicated video processors. As an industry partner he collaborated with Carnegie Mellon University to develop early High Level Synthesis tools, and also worked with UC Berkeley on several models of computation and dataflow computing. He was a director of architecture at Trimedia, and CTO at Chameleon Systems. For more than a decade, Kees has headed a team of researchers at Xilinx in Europe and the US, working on next generation programming environments for processors and FPGA fabric, high-performance video systems, machine learning applications and architectures, wireless applications and new datacenter applications. Kees has been instrumental in the High-Level Synthesis technology and is one of the technical leads for the novel ACAP technology.
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