June 10, 2003 in Social Responsibility News

SAMSUNG Electronics Presents Next Generation Nanometer Technologies at 2003 Symposium on VLSI Technology

Seoul, Korea, June 10, 2003: Samsung Electronics Co., Ltd., the world’s leader in advanced semiconductors, today announced a broad range of next generation semiconductor technologies at the prestigious 2003 Symposium on VLSI Technology at Kyoto Japan, June 10-14.

This year Samsung presents a vast 22 papers out of the 166 contributed papers, introducing recess-channel-array transistor technology for improved DRAM data retention time, CMOS based Phase-change RAM (PRAM), 90 nanometer (nm) NOR Flash memory cell, high density embedded SRAM cell, and core SoC process technologies for 65nmand beyond.

“ With the commercial production on 90nm circuitry impending, nano-scale technologies are the key interest at the 2003 VLSI Symposium”, said Ho-Kyu Kang, vice president of Advanced Process Development Project at Samsung Electronics, “Samsung’s dedication and advancements in next-generation technologies are reflected in the variety of papers that introduce the industry leading 90nm fabrication and 65nm process technologies.”

At the highlight session, Samsung introduces the successful development of a recess-channel-array transistor, a non-planar array transistor that improves the DRAM data retention time. This technology brings post bake yield rates up to 80-90 percent against the conventional 30-50 percent and can be easily adapted to 70nm or smaller geometries.

A prominent candidate for next generation memory, PRAM is introduced. Developed on CMOS technology, Samsung’s PRAM features reliable memory characteristics such as hot temperature operation, endurance against repetitive phase transition, reading disturbance, writing imprint effect and retention.

Samsung expands its memory technology as it introduces the industry’s smallest NOR Flash memory cell. Designed on 90nm line width, the NOR cell is achieved through utilizing KrF lithography and optimizing tunnel ox scaling and channel doping technologies.

Furthermore, Samsung introduces the development of advanced SoC designs. The industry’s smallest embedded SRAM cell, achieved on 90nm CMOS logic design, enables cost efficient applications of higher memory densities. And the development of high-K gate dielectric transistor technology delivers the industry’s most advanced low-power SRAM

Samsung extends its R&D expertise in next generation SoC process technologies such as advanced Ta-doped Ni salicide technology for future 30nm circuitry, low temperature ALD-SiO2, ALD-SiN and Low-k/Cu technologies for high performance devices, high-k MIM capacitor technology for mixed signal SoC designs, and a non volatile memory, dubbed Localized ONO Memory, for nano-scale embedded memories.

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