Samsung Foundry has qualified 32nm Low Power, High-K Metal Gate in Jun, 2010 which was the first HKMG product in foundry industry. Combining HK/MG with Gate first technology realized both extreme high performances and high area efficiency even without drastic changes in Poly-Si based conventional design methodology. 32nm HKMG process boasts up 30% higher speed, 30% less power, 30% scaling with twice of SRAM density over 45nm technology, making it ideal for high performance mobile applications. 32nm process is developed with abundant design ecosystem suitable for high performance mobile applications.
28nm Process Technology Meeting the Needs of Low-Power, High-Performance SoC Designs
Samsung's 28nm Low-Power High-K Metal Gate Process is built on two years of development and successful high-volume production of the 32nm LP HKMG process technology for a remarkably simple migration path.
Due to the complexity of multi-patterning and the introduction of FinFET transistors at 14nm, 28nm low-power High-K Metal Gate (HKMG) is expected to be a long-lived node with multiple product generations developed on this process. To address the growing need for different variations of the process, Samsung Foundry has broadened its portfolio to include the following offerings:
- 28nm RF Process Technology
Samsung foundry offers chip designers the ability to integrate advanced RF functionality into their designs for connectivity applications, which is 28RF process technology. Through the collaboration with EDA partners, 28RF process design kit (PDK) and verification method has been released to several customers, which has been proven by simulation and silicon results in real design.
Key Features of 28nm
- 28nm LPS : p-SiON for cost-sensitive applications that includes an easy migration path from older process nodes
- 28nm LPP : 2nd generation HKMG for greater power-efficiency in mobile and consumer electronic devices
- 28nm LPH : 2nd generation HKMG process for high performance application that is also energy efficient
- 28nm FD-SOI : higher-performance, lower-power for faster, cooler, simpler SoC designs
- Thin gate oxide for Core devices and Thick gate oxide for I/O devices
- Wire-bond pads or controlled collapse chip connections (C4s)
- Optional electrically programmable fuses (polysilicon e-Fuse)
|Core VDD (V)||1.0V||1.0V||0.9V||1.05V|
|SRAM||Single Port||HS, HD||HS, HD||HS, HD||HS|
* HS : High speed, HD : High Density