Samsung Foundry's 32/28nm Low-Power (LP) Gate First High-k Metal Gate (HKMG) process offers considerable power and performance advantages to a growing spectrum of mobile and IT infrastructure computing applications. Virtually all mobile applications relying on batteries and extremely tight power budgets demand 32/28nm LP solutions. But, low-power solutions are no longer limited to mobile applications. Reducing power is now a concern across a wide set of applications such as communications, networking, servers, and data centers.
Samsung Foundry has qualified 32nm Low Power, High-K Metal Gate in Jun, 2010 which was the first HKMG product in foundry industry. Combining HK/MG with Gate first technology realized both extreme high performances and high area efficiency even without drastic changes in Poly-Si based conventional design methodology. 32nm HKMG process boasts up 30% higher speed, 30% less power, 30% scaling with twice of SRAM density over 45nm technology, making it ideal for high performance mobile applications. 32nm process is developed with abundant design ecosystem suitable for high performance mobile applications.
Samsung's 28nm low power High-K Metal Gate Process is built on two years of development and successful high-volume production of the 32nm LP HKMG process and is designed for a remarkably simple migration path. The 28nm process is a gate-first High-K Metal Gate process which enables it to deliver significant performance while maintaining low power, making it ideal for mobile applications. A variant of the process, 28nm LPH HKMG, offers even greater power savings or performance boost beyond 2GHz. 28LP process is ideal for mobile applications where the low standby power is crucial, the high performance 28LPH process is a solution for more performance oriented applications that require extremely high performance incorporated with high energy efficiency. It boasts more than 20% speed over 28LP at the same standby power.
Key Features of 32/28nm
- Gate-First High-K Metal Gate stack
- Four 1.0V devices with thin gate oxide
- 1.5V / 1.8V device with thick gate oxide
- Six to ten copper metal layers Including up to six 1x level, two 2x level and two 8x metal levels
- Wire-bond pads or controlled collapse chip connections (C4s)
- Optional electrically programmable fuses (polysilicon e-Fuse)
|Core VDD (V)||1.0V||1.0V||0.9V|
|1.8V I/O Device||1.5V||•||•||•|
|2.5V I/O Device||2.5V||•|
|SRAM||Single Port||HS, HD||HS, HD||HS, HD|
* HS : High speed, HD : High Density