DDR2 SDRAM
Data Valid Window on DLL-Off Mode (October 2009)
DDR2 DIMM Test Point (August 2008)
User guide for using Parity DIMM on Non-parity system (October 2006)
ODT(On Die Termination) Control (March 2006)
Implementation "Dummy Pad" on the module PCB (March 2006)
DDR2 ODT Control (December 2004)
SPD for DDR2 SDRAM Module (May 2004)
DDR2 SDRAM tRFC (May 2004)
Low Power Feature (November 2003)

DDR SDRAM
DDR1 Industrial Thermal Application (March 2005)
Industrial Temperature (April 2004)
Non ECC Unbuffered DIMM Gerber (Raw Card "D", "E") (November 2003)
Point to Point Application (November 2003)
tRAS Lock-out & Concurrent Auto-Precharge (November 2002)
PC3200 DIMM(DDR400)SPD Program (June 2002)
DDR Registered DIMM current calculation method (June 2002)
Low power mode for DDR registered DIMM (November 2001)
tWR(Write recovery time) 15ns for DDR SDRAM (November 2001)
Basic DDR SDRAM Operations (November 2001)
Key points for controller design (November 2001)

Mobile SDRAM
Mobile DRAM's Frequently violated parameters Application Note (August 2009)
General PCB Design Guidelines for Mobile DRAM (August 2009)
ARM PrimeCell™ MPMC(PL172) Register Setting for Mobile SDRAM (September 2005)
Making higher density SDRAM with low power feature (August 2004)
Consideration for Timing Compensation in tR/tF (July 2003)
Driver Strength Control (March 2003)
[DPD]The strongest method to reduce SDRAM Power Consumption (November 2002)
[TCSR] How to reduce Self Refresh Current according to temperature changes. (November 2002)

RDRAM™
Max # of PC1066 RDRAM at i850e chipset board (November 2002)
256/288Mb A die : PC800 40ns vs. 45ns (April 2002)

SDRAM
High Speed(over 166MHz) SDRAM (November 2001)
3.3V Super Lowe Power SDRAM (November 2001)
512MB SDRAM SODIMM (November 2001)
SDRAM DIMM Write Protection (November 2001)
256M SDRAM Refresh Definition (November 2001)
tDAL Definition (November 2001)
PC133 Specification (November 2001)
PC133 SODIMM Status (November 2001)

Graphics DRAM
Graphic memory Dout valid window at DLL-off mode (November 2009)
16Mx32 GDDR3 I-die description (October 2009)
Dout Valid Window at DLL-Off Mode (February 2009)
64Mx16 gDDR3 Compatibility (January 2009)
32Mx32 GDDR3 90MHz Compatibility (May 2008)
32Mx32 GDDR3 1GHz Setting (May 2008)
GDDR1/2/3 Dout Valid window@DLL-off mode (June 2005)
Clock frequency change sequence (April 2005)
Clock frequency change sequence (March 2005)
The comparison of 8Mx32 GDDR F-die and F'-die in view of tRP/tWR/tWR_A/tDAL (March 2005)
GDDR2 ODT Control Method ( Single / Dual Rank) (November 2003)
Key Differenence between GDDR2 and GDDR3 (November 2003)
x32 GDDR/GDDR2 Operation at DLL-off mode (November 2003)
How to use Single CS 32M SGRAM in Dual CS System (like Voodoo3) (November 2002)
How to implement DDR SGRAM in Graphic System (November 2002)
Refresh Cycle change from 4K/64ms in C-die to 2K/32ms in 16M SDRAM D-die (November 2002)
The difference between tRDC 1CLK and 2CLK (November 2002)
How to keep the interchangeability among different density SGRAM (November 2002)
Address Matching in 8/16/32Mb SGRAM for backward compatibility (November 2002)
16M SGRAM based SODIMM Address Translation Table (November 2002)
x32 DDR 600Mbps Board Design Guidance (Point to Point Application) (November 2002)
x32 DDR SDRAM Usage Guidance (For Low Frequency Users) (November 2002)

UtRAM
UtRAM and UtRAM2's Frequently violated parameters (August 2009)
MRS/ CRE setting issues of UtRAM and UtRAM2 (August 2009)
TNAL060817_128Mb M&A comparison (August 2007)
TN0611_Row boundary Crossing (April 2007)
TNAL070117_SRAM Mode Comparison (January 2007)
Software MRS for UtRAM (November 2006)
TNAL060728_Power Up (status & current) (August 2006)
TNAL060613_tBC(Burst Cycle) (June 2006)
TNAL060622_Write method & Mode change (June 2006)
TNAL060622_Write method & Mode change_Mux (June 2006)